1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to a semiconductor memory device comprising two bit lines one for writing and the other for reading and two word lines one for writing and the other for reading for each memory cell, which device is represented by a serial access memory.
2. Description of the Background Art
Some semiconductor memory device includes memory cells, data of which is written and read through different paths. Such a semiconductor memory device is represented by a serial access memory.
In a serial access memory, data serially inputted bit by bit is written in a memory cell array in the order of addresses and the data is serially read bit by bit in the order of address from the memory cell array.
FIG. 10 is a schematic block diagram showing an entire arrangement of a conventional serial access memory.
Referring to FIG. 10, the serial access memory comprises a memory block 100 having memory cells arranged in matrix, a sense amplifier 102 for amplifying the data read from memory block 100, and a reading data buffer 104 for outputting the data amplified by sense amplifier 102 at an output terminal 106. The serial access memory further comprises a writing data buffer 110 for buffering the data inputted from a data input terminal 108 and applying the same to memory block 100, a writing address pointer 112 for rendering the memory cells in memory block 100 writable in the order of address during the data writing and a reading address pointer 114 for rendering the memory cells in the memory block 100 readable in the order of addresses during the data reading.
In the data writing, input data D.sub.0 -D.sub.n (n is a natural number) is applied to writing data buffer 110 through data input terminal 108. Writing data buffer 110 outputs the input data D.sub.0 -D.sub.n from data input terminal 108 bit by bit to memory block 100 in response to a writing clock signal WCK externally inputted from a writing clock terminal 116. At the same time, writing address pointer 112 renders the memory cells in memory block 100 writable in the order of address in response to the writing clock signal WCK such that each of the input data outputted from writing data buffer 110 is written in the memory cells in memory block 100 in the order of address. As a result, the input data is written row by row in the memory cells of memory block 100 in the order of address.
In the data reading, reading address pointer 114 selects the memory cells of memory block 100 in the order of address and renders the same readable in response to a reading clock signal RCK externally applied to a reading clock terminal 118 and activates sense amplifier 102. As a result, after the data is outputted from the memory cells of memory block 100 in the order of address, the data is amplified by sense amplifier 102 to a predetermined level. Then, reading data buffer 104 outputs each of data Q.sub.0 -Q.sub.n amplified by sense amplifier 102 in a predetermined cycle at data output terminal 106 in response to the reading clock signal RCK. In this way, the storage data of memory block 100 is extracted row by row in the order of address at data output terminal 106.
The specific arrangement of memory block 100 will be described. FIG. 11 is a partial circuit diagram showing the internal arrangement of memory block 100.
Referring to FIG. 11, in memory block 100, each of memory cells 1 is provided between a writing bit line 3 and a reading bit line 4 to constitute a memory cell column. At the same time, the adjacent memory cells in a row direction are connected to the same writing word line 5 and reading word line 6 to constitute a memory cell row.
Connected between each reading bit line 4 and a power supply line 19 supplied with a voltage Vcc of a logical high "H" level from a power supply (not shown) is an N channel MOS and a transistor 7 as a precharging transistor for precharging reading bit line 4 to a potential of a "H" level.
Precharging transistor 7 has a gate and a drain receiving the power supply voltage Vcc. Therefore, precharging transistor 7 is always turned on and when no data is read from memory cell 1, the transistor precharges reading bit line 4 by a voltage lower than the power supply voltage Vcc by a threshold voltage of the transistor.
Connected between each reading bit line 4 and reading address pointer 114 is an invertor 13 for inverting the potential on the reading bit line and two N channel MOS transistors 8a and 8b.
Each transistor 8a is provided between an input end of invertor 13 and sense amplifier 12, and each transistor 8b is provided between an output end of invertor 13 and sense amplifier 102. The gates of transistors 8a and 8b are connected together, which is connected to address pointer 114. Address pointer 114 has output terminals A.sub.0, A.sub.1, . . . A.sub.n corresponding to the respective reading bit lines 4 and the gates of transistors 8a and 8b provided corresponding to each reading bit line 4 are connected to the output terminals A.sub.0 -A.sub.n, respectively. Address pointer 114 sequentially outputs a voltage of a "H" level from the output terminals A.sub.0 -A.sub.n in response to the read clocking signal RCK to turn on the corresponding transistors 8a and 8b . Transistors 8a and 8b are reading bit line access transistors for transmitting the potential on the corresponding reading bit line and an inversed potential thereof, respectively, to sense amplifier 102 only in the on state.
Sense amplifier 102 amplifies the voltages of reading bit lines 4 provided corresponding to the transistors 8a and 8b to a predetermined level corresponding to the logical level and applies the amplified voltages to reading data buffer 104 by differentially amplifying the two voltages inputted through the transistors 8a and 8b.
Reading bit line 3 is connected to writing data buffer 110 of FIG. 10 and sequentially transmits the input data row by row to memory cell 1. Writing word line 5 is connected to writing address pointer 112 to receive, as writing word line selecting signal, potential for simultaneously rendering all the memory cells in a respective memory row data-writable. More specifically, writing address pointer 112 includes the same number (m) of output terminals B.sub.0 -B.sub.m as the number of writing word lines 5. These m writing word lines 5 are connected to output terminals B.sub.0 -B.sub.m, respectively, through diode-connected N-channel MOS transistors 90. Writing address pointer 112 outputs as a writing word line selecting signal, a "H" level potential to one of m output terminals B.sub.0 -B.sub.m. As a result, the potential of one of the m writing word lines 5 rises to a "H" level. Reading word lines 6 are sequentially driven one by one by address pointer 114. More specifically, the potential for rendering memory cell 1 data readable is applied as a reading word line selecting signal from address pointer 114 to only the reading word line 6 corresponding to the memory cell which data to be read (hereinafter referred to as the selected memory cell).
FIG. 12 is a circuit diagram showing the internal arrangement of memory cell 1.
Referring to FIG. 12, memory cell 1 comprises an N channel MOS transistor 14 having a gate connected to writing word line 5, an N channel MOS transistor 16 having a gate connected to reading word line 6, an N channel MOS transistor 15 and a memory capacitor 17. The transistors 15 and 16 are connected in series between reading bit line 4 and ground 18 and the transistor 14 is provided between writing bit line 3 and the gate of transistor 15. Memory capacitor 17 is provided between a node between the gate of transistor 15 and transistor 14 and ground 18. Reading bit line 4 is connected to a power supply line 19 through precharging transistor 7. The operation of this memory cell during data writing and data reading will be described below.
The data writing to memory cell 1 will be performed as follows.
The writing word line selecting signal causes the potential on writing word line 5 to attain a "H" level and a voltage of a "H" level or a "L" level is applied as input data to writing bit line 3. Writing word line 5 attains a "H" level to turn on transistor 14 and consequently a potential level of writing bit line 3, which is the input data, causes memory capacitor 17 to be charged or discharged to perform the write to memory cell 1. Namely, when the input data is at a "H" level, memory capacitor 17 is charged to cause the gate potential of transistor 15 to attain a "H" level and conversely, when the input data is at a "L" level, memory capacitor 17 is discharged to cause the gate potential of transistor 15 to attain a "L" level. Then, when the write is completed, writing word line 5 attains a "L" level to turn off transistor 14. However, the gate potential of transistor 15 is maintained at the attained level for a fixed time, (normally several hundreds mm seconds) by memory capacitor 17. In this way, the input data is stored in memory cell 1.
The data reading from memory cell 1 will be performed as follows.
The potential on reading word line 6 is set to a "H" level by the reading word line selecting signal to turn on transistor 16. As a result, reading bit line 4 is caused to have the potential corresponding to the conduction state of transistor 15. Namely, when "L" is written in memory cell 1, transistor 15 is in an off state, so that precharging transistor 7 supplies a high voltage from power supply line 19 to reading bit line 4, which line 14 attains a "H" level. Conversely, when "H" is written in memory cell 1, transistor 15 is in an on state. In this case, therefore, all of transistor 15 and 16 serially connected between power supply line 19 and ground 18 and precharging transistor 7 are in the on state, so that current (through current) is generated which flows between power supply line 19 and ground 18. Thus, the power supply voltage is supplied to reading bit line 4, which voltage is divided by a ratio of a sum of on-resistances of transistors 15 and 16 to the on-resistance of transistor 7. However, since transistors 15 and 16 are set to have larger current drivability than that of precharging transistor 7, the sum of the on-resistances is small enough to the on-resistance of transistor 7. Therefore, the potential on reading bit line 4 is lowered to a "L" level by a low potential 0 V of ground 18. In this way, in data reading, inversion of the storage data of memory cell 1 is read onto reading bit line 4.
The data read on reading bit line 4 is amplified (level sensing) by sense amplifier 102 of FIG. 10. The necessity and the operation principle of sense amplifier 102 will be described.
The potential on reading bit line 4 will be represented as follows in the cases where the storage data of memory cell 1 is at a "H" and a "L".
When the storage data of memory cell 1 is at a "H": ##EQU1## When the storage data of memory cell 1 is at a "L": EQU Vcc-Vth (2)
wherein, Vth denotes a threshold voltage of precharging transistor 7 and R7, R15 and R16 denote on-resistance value of precharging transistor 7, on-resistance value of transistor 15 and on-resistance value of transistor 16, respectively. According to the principle of the data reading from memory cell 1 to reading bit line 4 described above, the potential on reading bit line 4 is preferably a ground potential when the storage data of memory cell 1 is at a "H" and the potential of the same is preferably a power supply potential Vcc when the storage data of memory cell is at a "L". That is, a difference (which is referred to as a logical amplitude of the bit line) between the potentials on reading bit line 4, one of which potentials is when the storage data of memory cell 1 is at a "H" and the other is when the data is at a "L", is preferably as large as a difference between a power supply potential Vcc and a ground potential. However, as is clear from the above-described expression (1), when the storage data of memory cell 1 is at a "H", the potential on reading bit line 4 is higher than the ground potential (=0 V). On the other hand, as is clear from the above-described expression (2), when the storage data of memory cell 1 is at a "L", the potential on reading bit line 4 is lower than the power supply potential Vcc. Therefore, the logical amplitude of reading bit line 4 is considerably smaller than the difference between the power supply potential vcc and the ground potential. Therefore, it is difficult to determine whether the read data corresponds to logical values "0" or "1" if the potential on reading bit line 4 is simply inverted to be the reading data. Thus, sense amplifier 102 which is an amplifier of high sensitivity is required. Sense amplifier 102 is a differential amplifier inputting the potential on reading bit line 4 and a differential signal obtained by inverting the potential on reading bit line 4 by invertor 13.
Transistors 15 and 16 shown in FIG. 12 are referred to as a storage transistor and a reading transistor, respectively, in the following description.
FIG. 14 is a circuit diagram showing the internal arrangement of sense amplifier 102.
Referring to FIG. 14, sense amplifier 102 includes a series-connected circuit comprising a P channel MOS transistor TR2 and an N channel MOS transistor TR3 provided in parallel between power supply line 19 and ground 18 and a series-connected circuit comprising a P channel MOS transistor TR1 and an N channel MOS transistor TR4. The gates of transistors TR3 and TR4 are connected to the output ends of reading bit line 4 and invertor 13, respectively, in FIG. 10. The gates of transistors TR1 and TR2 are connected to the nodes between transistors TR2 and TR3 and the node between transistors TR1 and TR4, respectively. The potential 0 at the node between the transistors TR2 and TR3 and the potential 0 at the node between transistors TR1 and TR4 are applied to reading data buffer 104 as the output of this sense amplifier in FIG. 10.
In the data reading, the potentials of the complimentary logical levels represented by the above-described equations (1) and (2) are applied to the respective gates of transistors TR3 and TR4 from reading bit line 4 and invertor 13, respectively. When the gate potential of transistor TR3 is higher than that of transistor TR4, transistor TR3 is turned on, so that the source potential of transistor TR2 is lowered by the potential 0 V. In response thereto, transistor TR1 is turned on, so that the potential at the node between transistors TR1 and TR4 is raised by the power supply potential Vcc. Since the potential at the node between transistors TR1 and TR4 serves to turn off transistor TR2, the potential at the node between transistors TR2 and TR3 is reliably lowered to the ground potential 0 V. Thus, the potential at the node between transistors TR2 and TR3 ultimately attains the potential 0 V of ground 18 and the potential at the node between transistors TR1 and TR4 becomes the power supply potential Vcc. Similarly, when the gate potential of transistor TR4 is lower than that of transistor TR3, the transistor TR4 is turned on, so that the potential at the node between transistors TR2 and TR3 conversely becomes the power supply potential Vcc and the potential at the node between transistors TR1 and TR4 becomes the ground potential 0 V.
As the foregoing, this sense amplifier further lowers the potential of the "L" level represented by equation (1) to 0 V, further increases the potential of the "H" level represented by equation (2) to the power supply potential Vcc, which is developed at the node between transistors TR2 and TR3 and the node between transistors TR1 and TR4. In this way, the potentials at the two output ends of the sense amplifier are complimentarily changed in response to a gate potential difference between transistors TR3 and TR4 to output the power supply potential Vcc and the ground potential 0 V as the logical levels "H" and "L". Accordingly, the potential level read from memory cell 1 onto the corresponding reading bit line 4 in FIG. 11 is amplified by sense amplifier 102 to be output to reading data buffer 104.
Reading data buffer 104 is a circuit having a latching function which accepts the read data amplified by sense amplifier 102 at a predetermined timing in response to above-described reading clock signal RCK and outputs the same.
Again referring to FIG. 10, in the data reading, the inversion of the storage data is read from all the memory cells connected to reading word line 6 attaining a "H" level to the corresponding reading bit line 4. However, since only the reading bit line access transistors 8a and 8b provided corresponding to the reading bit line 4 connected to the selected memory cell are turned on, sense amplifier 102 is supplied with only the potential corresponding to the storage data of the selected memory cell.
FIG. 13 is a timing chart showing the operation of the serial access memory shown in FIG. 11 in data reading, taking as an example a case where the reading bit line 4 provided corresponding to one output terminal A.sub.0 of address pointer 114 is selected.
Referring to FIGS. 11 through 13, in the data reading, the output of a "H" level is sequentially outputted from the output terminals A.sub.0 -A.sub.n of address pointer 114 only in one cycle of the reading clock signal RCK in synchronization with a periodical rise of the reading clock signal RCK (FIG. 13(a)). Thus, the voltage of a "H" level is outputted from the output terminal A.sub.0 for example, in a (k-1)th (k=2, 3, . . . ) cycle period, of the reading clock signal RCK, as shown in FIG. 13(b). In the period when a signal of a "H" level is outputted from the output terminal A.sub.0, the data is read from the memory cell connected to the reading word line 6 supplied with a potential of a "H" level as a reading word line selecting signal and to the reading bit line 4 corresponding to the output terminal A.sub.0. Namely, when the storage data of this memory cell is at a "H", the potential on the reading bit line 4 corresponding to the output terminal A.sub.0 is lowered from a precharge potential (Vcc-Vth) to the potential (&gt;0 V) obtained by equation (1), as shown in FIG. 13(c). Thereafter, when data is read from the other memory cells connected to the reading bit line 4 and having the storage data of "L", the potential on this reading bit line 4 is gradually increased from the potential obtained by equation (1) to the precharge potential (vcc-Vth), as shown in FIG. 13(d). The potential on this reading bit line 4 is amplified by sense amplifier 102 by using the inversion potential thereof and then applied to reading data buffer 104. Meanwhile, reading data buffer 104 accepts the output of sense amplifier 102 in synchronization with the rise of the reading clock signal RCK. According, as shown in FIG. 13(e), the potential which reading bit line 4 ultimately attains during the period when the output of the output terminal A.sub.0 of address pointer 114 is at a "H" level is outputted to data output terminal 106 in one cycle (k-th) subsequent to the (k-1)th cycle period of the reading clock signal RCK. In this way, in a conventional serial access memory, the potential level read onto reading bit line 4 connected to the selected memory cell is sensed and all the other reading bit lines 4 are precharged to (Vcc-Vth), in one cycle period of the reading clock signal RCK.
The arrangement of reading address pointer 114 will be briefly described with reference to FIG. 15.
FIG. 15 is a circuit diagram showing the internal arrangement of address pointer 114.
Referring to FIG. 15, the address pointer includes (n +1) D flip-flops F0-Fn and two-input AND gates G0-Gn. Each D flip-flop accepts and holds a voltage applied to a data terminal D as data in synchronization with a rise (or a fall) of a clock signal applied to a clock terminal CK and outputs the same from an output terminal Q. Therefore, the change of the voltage applied to data terminal D is transmitted to each output of flip-flops F0-Fn with the delay by one cycle of the reading clock signal RCK.
Each of flip-flops F0-Fn has the clock terminal CK receiving the above-described reading clock signal RCK and the data terminal D receiving the output of the flip-flop in the preceding stage. Thus, the potential change at the data terminal D of the flip-flop F0 is sequentially transmitted to the output terminals Q of flip-flops F1-Fn, until the delay by one cycle of the reading clock signal RCK.
AND gates G0-Gn are provided corresponding to flip-flops F0-Fn, and receive the output of the corresponding flip-flops and the reading clock signals RCK as input. The outputs of AND gates G0-Gn are outputted to the output terminals A.sub.0 -A.sub.n of address pointer 114, respectively, in FIG. 10. Therefore, each of AND gates G0 -Gn outputs a signal voltage of a "H" level only when both the voltage developed at the corresponding output terminal Q and the reading clock signal RCK are at a "H" level. However, delay by one cycle of the reading clock signal RCK in the potential change at the output terminal Q of each of flip-flops F0-Fn appears at the output terminal Q of the flip-flop in the succeeding stage. Therefore, the signal voltage rendering the output of AND gates G0-Gn to a "H" level is transmitted to the output terminal Q of each of flip-flops F0-Fn with the delay by one cycle of the reading clock signal RCK, so that the output of AND gates G0-Gn sequentially attain a "H" level for a fixed period. As a result, reading bit line access transistors 8a and 8b provided corresponding to each reading bit line 4 are sequentially turned on for a fixed time period in FIG. 10.
As the foregoing, in the semiconductor memory device having two bit lines of a reading bit line and a writing line provided for each memory cell column represented by a conventional serial access memory, the precharging transistor for precharging a bit line is always in an on-state. Therefore, through current is increased during the data reading to cause such problems as follows.
Namely, in the serial access memory shown i FIG. 10, each of all the transistors 7 has a gate and a drain connected to power supply line 19 so that all the bit lines 4 are always electrically connected to power supply line 19 at any time. Therefore, the through current flows for a period when reading is carried out from power supply line 19 to ground 18 through a memory cell which storage data is at a "H" level among the memory cells 1 connected to the selected reading word line 6 during the data reading, that is, when the reading word line 6 is at a "H" level. For example, in the worst case, that is, where "H" is written in all the memory cells 1, through current flows from power supply line 19 to ground 18 through precharging transistor 7, reading bit line 4, storage transistor 15 and reading transistor 16 in all the memory cells connected to the reading word line 6 corresponding to the selected memory cell until the end of the reading in the period when any memory cell is selected. Namely, in such a case, the through current flows through all the reading bit lines at any time during the data reading.
If the through current is large, the ground potential attains a higher level than the original level (=0 V) or the power supply potential attains lower level than the original level Vcc to fluctuate levels of the ground potential and the power supply potential. It has already been found that such a fluctuation in potential level as a reference for the operation of the memory is one of the reasons of the reduced time for discharging memory capacitor 17 in memory cell 1, that is, the time for maintaining data of the memory cell, which should be avoided as much as possible. In addition, if the current flowing in the memory during the operation is large, power consumption of the memory is increased, so that the amount of heat generation of the memory chip containing the memory is increased or the power supply load of the entire system containing the memory is increased. Thus, it is desirable that such through current as described above is as small as possible.
Furthermore, if the storage data of the selected memory cell is at a "H", precharging transistor 7 is in the on state at any time during the data reading, whereby the corresponding reading bit line 4 is drawn to a low potential 0 V of ground 18 by storage transistor 15 and reading transistor 16 (see FIG. 12) in the selected memory cell, while a high voltage is supplied from power supply line 19 by precharging transistor 7 connected to the reading bit line 4. Therefore, it takes time for reading bit line 4 to attain a "L" level. In order to accurately output the storage data of the selected memory cell to sense amplifier 102 of FIG. 10, the potential level of the reading bit line 4 corresponding to the selected memory cell should attain the original level that should be attained (expressed by the above described equations (1) and (2)) corresponding to the storage data of the selected memory cell. Therefore, it is necessary to output the signal amplified by sense amplifier 102 after the reading bit line 4 attained the original level as the reading data to buffer 106. As the foregoing, reading bit line 4 takes time in attaining a potential of a "L" level, which means that it is difficult to rapidly read the data from the memory cell having the storage data of "H".
Referring to FIG. 12, when the storage data of memory cell 1 is at a "H", the potential on the corresponding reading bit line 4 is ultimately lowered to the level obtained by the above-described equation (1) by the through current but does not attain 0 V during the data reading from the memory cell 1. Therefore, the logical amplitude of the conventional serial access memory is small that a differential amplification type sense amplifier (FIG. 14) is used therein. However, arrangement of sense amplifiers allowing accurate amplification of two input voltages having a small voltage difference to a predetermined level requires very complicated adjustments of a threshold, a size of a transistor constituting the sense amplifier or the like in manufacture. Thus, a conventional serial access memory comprising a sense amplifier of a complicated arrangement is difficult to manufacture.
In recent years, especially as memories increase in capacity, the number of memory cells connected to one word line is increased, which results in large through current during data reading, causing such problems as described above.
In order to reduce the through current, proposed is a method of increasing an on-resistance value of precharging transistor 7 by reducing current drivability (size) of the precharging transistor 7 of FIG. 12. However, a reduced size of a precharging transistor causes the following problems.
For example, after data is read from a memory cell to cause the potential level on the corresponding reading bit line 4 to attain a "L", when data is read from the other memory cells connected to this reading bit line 4 and having the storage data of "L", this reading bit line 4 should rapidly attain a "H" level during the data reading to allow the data reading to be performed at a high speed. However, if the size of precharging transistor 7 is small, the current amount flowing from power supply line 19 through precharging transistor 7 to reading bit line 4 is reduced, so that more time is required for the potential level of the reading bit line 4 to rise to a "H" by the power supply voltage. Namely, since more time is required for the reading bit line 4 to be completely precharged to a "H" level by precharging transistor 7 (a time required for reading bit line 4 to attain the potential (Vcc-Vth) in FIG. 13(d)), it is not possible to immediately read the data from the memory cell connected to the reading bit line 4 once attaining a "L" level and having the storage data of "H".